hdlbits.01xz.net /circuits/sequential logic/finite state machines/design a moore fsm-爱代码爱编程
状态机图
成功代码:
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
reg [5:0] current_state;
reg [5:0] next_state;
parameter SNone = 6'b000001;
parameter S1Pos = 6'b000010;
parameter S1Neg = 6'b000100;
parameter S1S2Pos = 6'b001000;
parameter S1S2Neg = 6'b010000;
parameter S1S2S3 = 6'b100000;
always@(posedge clk) begin
if(reset) begin
current_state = SNone;
fr3 = 1;
fr2 = 1;
fr1 = 1;
dfr = 1;
end
else begin
current_state = next_state;
case(current_state)
SNone: begin
fr3 = 1;
fr2 = 1;
fr1 = 1;
dfr = 1;
end
S1Pos: begin
fr3 = 0;
fr2 = 1;
fr1 = 1;
dfr = 0;
end
S1Neg: begin
fr3 = 0;
fr2 = 1;
fr1 = 1;
dfr = 1;
end
S1S2Pos: begin
fr3 = 0;
fr2 = 0;
fr1 = 1;
dfr = 0;
end
S1S2Neg: begin
fr3 = 0;
fr2 = 0;
fr1 = 1;
dfr = 1;
end
S1S2S3: begin
fr3 = 0;
fr2 = 0;
fr1 = 0;
dfr = 0;
end
endcase
end
end
always@(*) begin
next_state = SNone;
case(current_state)
SNone: begin
if(s[1])
next_state = S1Pos;
else
next_state = SNone;
end
S1Pos: begin
if(s[2])
next_state = S1S2Pos;
else if(s[1] == 0)
next_state = SNone;
else
next_state = S1Pos;
end
S1Neg: begin
if(s[2])
next_state = S1S2Pos;
else if(s[1] == 0)
next_state = SNone;
else
next_state = S1Neg;
end
S1S2Pos: begin
if(s[3])
next_state = S1S2S3;
else if(s[2] == 0)
next_state = S1Neg;
else
next_state = S1S2Pos;
end
S1S2Neg: begin
if(s[3])
next_state = S1S2S3;
else if(s[2] == 0)
next_state = S1Neg;
else
next_state = S1S2Neg;
end
S1S2S3: begin
if(s[3]==0)
next_state = S1S2Neg;
else
next_state = S1S2S3;
end
endcase
end
endmodule
尝试1:
module top_module (
input clk,
input reset,
input [3:1] s,
output fr3,
output fr2,
output fr1,
output dfr
);
reg [5:0] current_state;
reg [5:0] next_state;
parameter SNone = 6'b000001;
parameter S1Pos = 6'b000010;
parameter S1Neg = 6'b000100;
parameter S1S2Pos = 6'b001000;
parameter S1S2Neg = 6'b010000;
parameter S1S2S3 = 6'b100000;
always@(posedge clk, posedge reset) begin
if(reset)
current_state = SNone;
else
current_state = next_state;
end
always@(*) begin
next_state = SNone;
case(current_state)
SNone: begin
if(s[1])
next_state = S1Pos;
end
S1Pos: begin
if(s[2])
next_state = S1S2Pos;
if(s[1] == 0)
next_state = SNone;
end
S1Neg: begin
if(s[2])
next_state = S1S2Pos;
if(s[1] == 0)
next_state = SNone;
end
S1S2Pos: begin
if(s[3])
next_state = S1S2S3;
if(s[2] == 0)
next_state = S1Neg;
end
S1S2Neg: begin
if(s[3])
next_state = S1S2S3;
if(s[2] == 0)
next_state = S1Neg;
end
S1S2S3: begin
if(s[3]==0)
next_state = S1S2Neg;
end
endcase
end
always@(*) begin
case(current_state)
SNone: begin
fr1 = 1;
fr2 = 1;
fr3 = 1;
dfr = 1;
end
S1Pos: begin
fr1 = 1;
fr2 = 1;
fr3 = 0;
dfr = 0;
end
S1Neg: begin
fr1 = 1;
fr2 = 1;
fr3 = 0;
dfr = 1;
end
S1S2Pos: begin
fr1 = 1;
fr2 = 0;
fr3 = 0;
dfr = 0;
end
S1S2Neg: begin
fr1 = 1;
fr2 = 0;
fr3 = 0;
dfr = 1;
end
S1S2S3: begin
fr1 = 0;
fr2 = 0;
fr3 = 0;
dfr = 0;
end
endcase
end
endmodule